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An 84-mW 4-Gb/s Clock and Data Recovery Circuit for Serial Link Applications M.-J. Edward Lee1,3, William J. Dally1,3, John W. Poulton2,3, Patrick Chiang1, and Stephen F. Greenwood1 1Stanford 2UNC
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City

Hill / San Jose / /

Company

National Semiconductor / Intel Corporation / USA Communications Inc. / /

Country

United States / /

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Facility

Sitterson Hall Chapel / Serra Mall / Chapel Hill CB / /

Organization

Chiang1 / and Stephen F. Greenwood1 1Stanford 2UNC University / United States Army / Stanford / /

Person

Dean Liu / Ramin Farjad-Rad / Mark Horowitz / Jaeha Kim / /

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Position

central phase controller / Receive Amplifiers Peripheral Loop Multiphase DLL Phase Controller / phase controller / Senator / controller / /

ProvinceOrState

North Carolina / California / /

Technology

0.24µm CMOS technology / finite state machine / CAD / /

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