Semiconductor Research Corporation / TGPL / ACSEL Laboratory / Fujitsu Ltd. / Intel / Integration Corp. / Fujitsu Laboratories of America / /
Country
United States / /
Currency
USD / / /
Facility
Pipeline Stage Energy / University of California / /
IndustryTerm
minimum energy consumption / logic block energy / energy target / low energy characteristics / energy characteristics / delay product / even energy-efficient characteristics / energy evaluation / particular sizing solution / low energy / similar energy spending / energy-efficient design points / energy penalty / energy range / energy-minimized points / energy delay optimization / fixed energy / energy targets / given technology / minimum energy designs / energy-efficient general-purpose storage element topology / energy-efficient characteristics / energy break / lower energy consumption / large clock energy consumption cost / energy measurement / energy consumption target / high energy sensitivity region / large energy / composite energy / Pipeline-stage energy / energy savings / equivalent energy / energy results / energy / minimum energy envelope / low energy designs / large energy consumption / energy consumption / classic energy / average energy / actual energy-efficient designs / energy cost / energy characteristic / non-energy-efficient designs / technology scaling / low-power processor / energy saving / energy characteristic results / energy budget / energy efficient characteristics / energy-efficient characteristic / energy-minimized envelope / pipeline register energy quantification / composite energy-efficient characteristic / energy efficient characteristic / smallest energy / /
Organization
University of California / Davis / /
Person
Semi-Dynamic Flip-Flop / Nikola Nedovic / Christophe Giacomotto / /