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Hardware verification languages / Aldec / Logic design / Hardware emulation / Hardware description languages / Field-programmable gate array / Joint Test Action Group / Mentor Graphics / Application-specific integrated circuit / Electronic engineering / Electronic design automation / Digital electronics


HES-DVM™ HW/SW Validation Platform Hybrid Verification Platform HES-DVMTM is a Hybrid Verification and Validation Platform for Hardware and Software developers of SoC and ASIC designs up to 144M ASIC gates. Utilizing
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Document Date: 2015-02-02 17:14:32

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File Size: 454,41 KB

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Company

Virtual Platform / Aldec Inc. / Xilinx / SCE-MI Hardware / /

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Event

FDA Phase / /

Facility

library Prototyping Testbench Co-Simulation Interface / /

IndustryTerm

speed emulation solution / embedded systems / real-time data / /

OperatingSystem

Microsoft Windows / XP / Linux / /

Organization

European monetary union / ASIC / SoC / /

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Product

AXI4-Lite / /

ProgrammingLanguage

C / C++ / /

Technology

DESIGN VERIFICATION / Server Farm / FPGA / ASIC / MEMS / Simulation / Linux / API / FPGA technology / HDMI / JTAG / GUI / Gigabit Ethernet / UART / /

URL

www.aldec.com / /

SocialTag