| Document Date: 2003-10-01 16:10:00
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City Run / IEEE / Loader / Specific Optimizations / Cold / Itanium / / Company Hewlett Packard / Intel / compiled using the Intel / / Currency USD / / Event Product Issues / FDA Phase / / IndustryTerm performancesensitive applications / hardware solution / solution technology / bi-directional protocol / processor family systems / technology model / code morphing software / Internet Content Creation part / nonperformance critical applications / binary translation technology / precise exception handling technology / dynamic binary translation software / software techniques / / MarketIndex TOP / / OperatingSystem Linux / Microsoft Windows / L3 / / Person Alex Skaletsky / Ronny Ronen / Leonid Baraz / Maggie Auerbach / Yun Wang / Orna Etzion / Laura Cane / Tevi Devor / Yigal Zemach / Shalom Goldenberg / Evelyn Duesterwald / / Position dynamic-static hybrid translator / PA-RISC* translator / block head / application-level binary translator / IEEE BTGeneric Initialize Translator / translator / Apply General / representative / scheduler / General / dynamic translator / head / dynamic binary translator / single translator / IEEE The translator / IA32 EL translator / / Product EL / instruction / IPF instruction / points / IA-32 instructions / instructions / assigning IA-32 EL / / ProgrammingLanguage Java / FP / C++ / / Technology Alpha / bi-directional protocol / Itanium processor / 2 processor / RAM / MMX™ technology / Java / Linux / API / solution technology / Itanium processors / binary translation technology / 1.6GHZ Xeon™ processor / operating system / underlying technology / operating systems / precise exception handling technology / /
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IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium®-based systems Leonid Baraz, Tevi Devor, Orna Etzion, Shalom Goldenberg, Alex Skaletsky, Yun Wang and Yigal Zemach.