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Appears in the ¿ Ø Annual International Symposium on Microarchitecture Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
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Document Date: 2006-10-26 23:09:43

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IBM / MT RT RT RT / OPN / RT RT RT ET / Computer Sciences / /

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Last store / External Store / store IDs / Store Queue ESN Miss Handler DSN OCN / Store ID EXIT / Computer Engineering The University of Texas / /

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external store network / nearest-neighbor networks / on-chip network / operand network / large processors / given bank / contention accounting / cache bank / streaming applications / control processor / conventional processor / control networks / wide-issue processors / memory disambiguation hardware / on-chip data networks / processor control networks / metal / mesh router / operand router / ultra-low-latency micronetwork routers / signal processing library / 8KB cache bank / control network / optimization algorithms / control protocols / bank / 64KB bank / software model / mesh network / inter-processor / microarchitectural protocols / distributed banks / 16KB bank / dispatch network / hardware protocols / distributed microarchitectural protocols / data status network / bypass network / microarchitectural networks / status network / prototype chip / /

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MT MT ET MT OCN MT MT MT MT MT MT PROC / MT ET ET ET ET ET ET ET ET PROC / /

Organization

University of Texas at Austin / ASIC / TRIPS Prototype Processor Karthikeyan Sankaralingam Ramadass Nagarajan Robert McDonald Rajagopalan DesikanÝ Saurabh Drolia M.S. Govindan Paul GratzÝ Divya Gulati Heather HansonÝ Changkyu Kim Haiming Liu Nitya Ranganathan Premkishore Shivakumar Simha Sethumadhavan Sadia SharifÝ Stephen W. Keckler Doug Burger Department of Computer Sciences ÝDepartment of Electrical / /

Person

Register Tile / Paul GratzÝ / Kim Haiming Liu Nitya Ranganathan / Heather HansonÝ / Stephen W. Keckler Doug Burger / /

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GT RT IT DT ET MT NT SDC DMA EBC C2C Chip / external bus controller / Prime Minister / callo RT / RT / ÙØ ÓÒ An RT / General / producer / controller / programmer / /

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C / /

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Montana / /

Technology

Alpha / CISC processor / 4-ported routers / TRIPS processor / control network / large processors / operand router / distributed protocols / microarchitectural protocols / two processors / 4-port routers / TRIPS processors / 21264 processor / SRAM / operating system / hardware protocols / wide-issue processors / control protocols / 4 Distributed Microarchitectural Protocols / DDR SDRAM / Higher-level microarchitectural protocols / ASIC / PowerPC processor / prototype chip / TRIPS chip / four-port mesh router / board-level PowerPC control processor / 16-issue conventional processor / optimization algorithms / TRIPS chips / 130 nm ASIC chip / SDRAM / simulation / distributed microarchitectural protocols / ÓÒ× The TRIPS chip / ultra-low-latency micronetwork routers / 130nm ASIC prototype chip / /

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www.cs.utexas.edu/users/cart / /

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