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Power optimization in current mode circuits M. S. Bhat and H. S. Jamadagni Centre for Electronics Design and Technology Indian Institute of Science, Bangalore[removed], INDIA {msbhat, hsjam}@cedt.iisc.ernet.in
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Document Date: 2010-09-19 00:21:23

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City

Victoria / /

Company

Cox / John Wiley and Sons Inc. / IDC / /

Country

India / Canada / /

Currency

USD / /

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Facility

Technology Indian Institute of Science / /

IndustryTerm

portable computing / signal processing / wireless communication / /

Organization

M. S. Bhat and H. S. Jamadagni Centre for Electronics Design / US Federal Reserve / Indian Institute of Science / Bangalore / /

ProgrammingLanguage

J / DC / /

ProvinceOrState

Victoria / /

Technology

ADC / Simulation / 0.7-Pm MIETEC CMOS technology / integrated circuits / flash / CMP / fuzzy logic / designed using 0.7-Pm MIETEC CMOS technology / /

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