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Integrated circuits / Semiconductor device fabrication / Constraint graph / Electronic design / Physical design / Placement / Floorplan / Through-silicon via / Cluster analysis / Electronic engineering / Electronic design automation / Electronics


Document Date: 2012-01-31 08:03:49

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Company

Gartner / Intel / /

Currency

AMD / USD / /

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Facility

Institute of Electromechanical / University of Michigan / Dresden University of Technology / /

IndustryTerm

nanoelectromechanical systems / networks-on-chip / insertion algorithm / local search / industrial chip / business to business / nm technology node / technology choices / microelectromechanical systems / clocktree-generation algorithms / metal layers / similar baseline algorithms / manufacturing process / energy / technology nodes / distinct manufacturing processes / net clustering algorithm / high metal layers / valid solution / heterogeneous manufacturing processes / manufacturing / place-and-route tools / valid solutions / /

OperatingSystem

Linux / /

Organization

University of Michigan / Ann Arbor / Institute of Electromechanical / Institute of Electromechanical and Electronic Design / German Research Foundation / Department of Electrical Engineering and Computer Science / Dresden University of Technology / Dresden / /

Person

Jens Lienig / Igor L. Markov / Johann Knechtel / /

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Position

Editor / hb / wb / representative / /

Product

L2Di / /

ProgrammingLanguage

C++ / /

PublishedMedium

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS / /

Technology

RAM / chip design / TSV-island insertion algorithm / 3-D / Linux system / 3-D Chips / similar baseline algorithms / time algorithm / net clustering algorithm / clocktree-generation algorithms / lithography / SRAM / 2.4 GHz AMD Opteron processor / INTEGRATED CIRCUITS / 2-D chips / 2 processor / microelectromechanical systems / MEMS / radio frequency / Digital Object Identifier / F2B technology / /

URL

http /

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