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Electronic design automation / Combinatorial optimization / Floorplan / Integrated circuit / Dynamic random-access memory / Yield / Module / Electronic engineering / Mechanics / Physics


IEEE TRANSACTIONS ON COMPUTERS, VOL. 49, NO. 6,
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Document Date: 2011-01-27 16:46:18

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File Size: 543,37 KB

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yield-oriented floorplanning algorithm / clear-cut solution / greedy constructive algorithm / constructive algorithm / designed chip / rectangular chip / processor chip / manufacturing defects / high manufacturing volume memory / possible solution / constructive floorplanning algorithm / half-chip / heuristic algorithms / given floorplanning algorithm / manufacturing / square chip / /

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