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Digital electronics / Hardware verification languages / Logic design / SystemVerilog / Verilog / Synopsys / E / Verilator / Flow to HDL / Electronic engineering / Electronic design automation / Hardware description languages


sutherland-hdl_workshops.fm
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Document Date: 2012-11-02 18:47:30

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File Size: 26,72 KB

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City

Tualatin / Reading / /

Company

Sutherland HDL Inc. / Synopsys / Mentor Graphics / RTL / /

Currency

USD / /

IndustryTerm

online materials / live online class / example solutions / synthesis tools / /

Organization

ASIC / /

Person

Stuart Sutherland / Lab / /

/

Position

model / President / design engineer / General / /

ProgrammingLanguage

Verilog / DC / Hardware Description Language / /

ProvinceOrState

Oregon / /

Technology

Design Verification / FPGA / RAM / ASIC / Verilog / embedded DSP processor / simulation / DSP processor / DSP / UART / /

URL

www.sutherland-hdl.com / /

SocialTag