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Formal methods / Physical design / SystemVerilog / Synopsys / Formal verification / Verilog / Formal equivalence checking / Signoff / Electronic engineering / Electronic design automation / Hardware description languages


Datasheet Formality and Formality Ultra Equivalence Checking for DC Ultra and Design Compiler Graphical Overview
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Document Date: 2015-02-18 15:15:30

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File Size: 1,48 MB

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Company

Formality Ultra Key Benefits Formality Ultra / RTL / Red Hat / Synopsys Inc. / /

Country

United States / /

IndustryTerm

equivalence checking solution / /

OperatingSystem

ECOs / Suse / Solaris / Linux / /

Organization

International Criminal Court / /

/

Position

Platform Support designer / ECO designer / history and common text editor / designer / local sales representative / /

ProgrammingLanguage

DC / Verilog / /

Technology

ESP technology / Verilog / VHDL / Linux / Hier-IQ technology / ASCII / GUI / /

URL

www.synopsys.com / http /

SocialTag