| Document Date: 2007-11-14 11:05:31
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City Monterey / New York / / Company Triple-DES Cryptography / SYNOPSYS / Reconfigurable Hardware / XILINX / TWOFISH / the AES / / Country Belgium / United States / / Currency USD / / / Event Reorganization / / Facility National Institute of Standards and Technology / Pipeline AES Rijndael / / IndustryTerm software implementations / synthesis tool / software ones / synthesis tools / candidates algorithms / encryption algorithms / / Organization FPGA Board / National Institute of Standards and Technology / Triple-DES Using SLAAC-1V FPGA Accelerator Board / / Person Joan Daemen / Algorithm Finalists / Vincent Rijmen / Jean-Didier Legat / Jean-Jacques Quisquater / François-Xavier Standaert / / / Position General / designer / Candidate / / Product VIRTEX1000BG560-6 / VIRTEX3200ECG1156-8 FPGA / / ProvinceOrState New York / California / / PublishedMedium Lecture Notes In Computer Science / / Region Levant / / Technology FPGA / RAM / s/N / encryption algorithms / Data encryption / block cipher / High encryption / 15 candidates algorithms / RIJNDAEL encryption / VHDL / RIJNDAEL algorithm / Encryption / Cryptography / VIRTEX-E technologies / same technology / key scheduling algorithm / http / Gigabit / described using VHDL / / URL http /
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A Methodology to Implement Block Ciphers in Reconfigurable Hardware and its Application to Fast and Compact AES RIJNDAEL François-Xavier Standaert, Gael Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat