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 Date: 2016-03-22 12:43:37Computing Computer architecture Electronic engineering VHDL ModelSim Field-programmable gate array ARC Synopsys Router |
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Date: 2016-03-22 12:43:37Computing Computer architecture Electronic engineering VHDL ModelSim Field-programmable gate array ARC Synopsys Router |
Add to Reading List |
Transactor-based debugging of massively parallel processor array architectures Markus Blocherer, Srinivas Boppu, Vahid Lari, Frank Hannig, Jürgen Teich Hardware/Software Co-Design University of Erlangen-Nuremberg