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Altos Design Automation / Mentor Graphics / Synopsys / Static timing analysis / Verilog / Electronic circuit simulation / SPICE / Electric / Cadence Design Systems / Electronic engineering / Electronic design automation / Software


Liberate LV Improve your view… Liberate LV provides a collection of utilities for validating libraries including functional equivalence checking, data consistency checking, revision analysis and correlation with variou
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Document Date: 2009-07-14 19:09:50


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City

San Jose / /

Company

Mentor Graphics Inc. / Extreme DA Inc. / Synopsys Inc. / Incentia Inc. / Cadence Design Systems Inc. / /

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Facility

Library Validation / library Verilog / /

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IndustryTerm

electrical analysis tools / large computer network / appropriate analysis tool / generation tools / downstream tools / Statistical timing analysis tools / software version incompatibilities / characterization systems / manufacturing / supports multiple analysis tools / characterization tool / /

OperatingSystem

CentOS / Solaris / Linux / /

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Product

TimeCraft / /

ProgrammingLanguage

HTML / Verilog / /

ProvinceOrState

California / /

Technology

Verilog / simulation / HTML / Linux / /

URL

www.altos-da.com / /

SocialTag