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City Baltimore / / Company Distributed Systems / FPGAs / GPUs / Johns Hopkins University Press / Altera / Parallel / GPU / Reconfigurable Systems / HP / Nvidia / Intel / Xilinx / Microsoft / / Country United States / / Currency AMD / / / Facility port RAM / Intel Math Kernel library / port p. / Gaxpy Pipeline / Gaxpy Architecture A Gaxpy pipeline / CUDA BLAS library CUBLAS / / IndustryTerm bank assignment module / performance computing / hardware/software co-design frameworks / scientific applications / bank-interleaved vector memory / numerical linear algebra applications / times better energy efficiency / row banks / point operator / dot product / configurable hardware / banked memory systems / energy efficient climate supercomputer / measurement infrastructure / particular row bank / update algorithm / bank assignment switch / energy / row bank / scientific computing community / bank interleaving / bank / educational devices / quad core processor / bank assignment / higher energy efficiency / dot-product / row-bank / embedded processors / point applications / energy efficiency / computing / non-traditional computing platforms / sum-of-products / linear systems / scientific computing / / OperatingSystem Windows Server 2008 / / Organization ON V / Johns Hopkins University / US Federal Reserve / IEEE Computer Society / The Pennsylvania State University University / / Person Max Variance / John D. Davis / BLAS L EVEL / Oliver Williams / / / Position driver / Feed-forward / The Feed-forward / / Product BEE3 / / ProgrammingLanguage RC / C / Verilog / Joule / / ProvinceOrState Manitoba / / PublishedMedium IEEE Transactions on Computers / / Technology FPGA / RAM / molecular modeling / cache memory / SRAM / html / pdf / 2 Duo E8500 processor / Verilog / matrix multiplication using rank-1 update algorithm / http / flash / / URL http /
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BLAS Comparison on FPGA, CPU and GPU Srinidhi Kestur† † John D. Davis‡