| Document Date: 2006-03-07 18:19:07
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City Newport Beach / / Company Integrated Systems Laboratory / / Facility Integrated Systems Laboratory / SWISS FEDERAL INSTITUTE OF TECHNOLOGY ZURICH / Library Cells / / IndustryTerm digital signal processors / metal / digital signal processor / technology aspects / carry-in processing / versatile synthesis algorithms / universal algorithm / heuristic algorithms / layout design technologies / synthesis algorithms / Elaborate efficient and versatile synthesis algorithms / data-processing application-specific / non-heuristic algorithm / / Organization ASIC / Central Intelligence Agency / SWISS FEDERAL INSTITUTE OF TECHNOLOGY ZURICH / Swiss Government / / Person Christoph Wicki / Norbert Felber / W. Fichtner / Lothar Thiele / Duncan Fisher / Rajiv Gupta / Wolfgang Fichtner / Andreas Wieland / Adam Feigin / L. Thiele / / Position advisor / CPA / Direct CPA / Compound CPA / General / / ProvinceOrState California / / Technology FPGA / non-heuristic algorithm / ASIC / VLSI chip / synthesis algorithms / 5.3 Tree-prefix algorithms / 25 3.5 Prefix Algorithms / one universal algorithm / 5.2 Serial-prefix algorithm / Synthesis Algorithm / versatile synthesis algorithms / key layout design technologies / DSP / digital signal processors / integrated circuits / digital signal processor / integrated circuit / /
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Diss. ETH NoBinary Adder Architectures for Cell-Based VLSI and their Synthesis A dissertation submitted to the