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Reconfigurable computing / Parallel computing / Central processing unit / Microprocessors / Tensilica / Field-programmable gate array / Instruction set / LEON / Reconfigurability / Computer architecture / Computer hardware / Electronic engineering


A Quick Safari Through the Reconfiguration Jungle Patrick Schaumont Ingrid Verbauwhede Majid Sarrafzadeh
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Document Date: 2003-06-11 14:31:52


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City

Las Vegas / San Diego / /

Company

Atmel / Altera / Actel / PMC-Sierra / Morphics / RTL / Stanford University Compiler Group / /

Country

United States / /

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Facility

Machine SUIF SUIFvm Library / University of California / Harvard University / /

IndustryTerm

age processing / elliptic curve crypto-processor / reconfigurable devices / design technology support / low energy / reconfigurable computing / implemented using hardware / wireless communication applications / representative algorithms / configurable systems / autonomous devices / semiconductor processing / wireless communications / configurable devices / system design technologies / configurable applications / signal processing / programmable systems / synthesis tools / agreement protocol / reconfigurable systems / deep submicron technologies / iterative image restoration algorithm / wireless base-station market / configurable computing / domain specific processors / configurable processors / packet processing / route tools / hierarchical systems / image processing / reconfigurable kernel processing elements / result reconfigurable technology / software environment / design technology / lowest processing level / multi-processor / detection operators / stand-alone reconfigurable devices / encryption algorithm / co-processor / elliptic curve multiplication algorithm / /

Organization

UCLA / Harvard University / Division of Engineering and Applied Systems / Computer Science Department / ASIC / Stanford University / University of California / Los Angeles / /

Person

Seda Ogrenci / Hui Zhang / William H. Maggione-Smith / Majid Sarrafzadeh / Potkonjak Maggione-Smith / Dave Garrett / Jan Rabaey / Glenn Holloway / Michael D. Smith / Ingrid Verbauwhede / /

Position

AR/T Designer / Configurable Design Elements Communication Storage Processing Implementation Switches Muxes RAM Organization CLB Parametrizable IP-block Micro-Architecture Crossbar Busses Register File Size Cache Architecture Execution Unit Type Interpreter / interpreter / IC designer / designer / use model for these systems / representative / hierarchical controller / AVR micro-controller / controller / actual programmer / /

Product

FPSlic / /

ProgrammingLanguage

Fortran / C++ / /

ProvinceOrState

California / /

RadioStation

Core / Word 1 / /

Technology

semiconductor / Configurable System-on-a-Chip / FPGA / virtual machine / RAM / Av / deep submicron technologies / Xtensa processors / JPEG / on chip / individual VLIW Jazz processor / encryption algorithm / CDMA / wireless communications / key agreement protocol / DSP processors / design technology / queuing algorithm / system-on-a-chip / domain specific processors / programmable DSP processors / secret key / iterative image restoration algorithm / elliptic curve multiplication algorithm / image processing / VHDL / VLIW processors / Jazz processors / encryption / result reconfigurable technology / cryptography / ASIC / adpcm / system design technologies / public key / elliptic curve crypto-processor / Elliptic Curve Encryption Processor / cdma2000 Chip / DSP / Voice-over-IP / Diffie-Hellmand key agreement protocol / MediaBench file name/reconfigurable Algorithms / CAD / /

URL

http /

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