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Computer architecture / Central processing unit / Dynamic random-access memory / Digital electronics / Field-programmable gate array / Cell / Parallel computing / Microprocessor / CPU cache / Computer hardware / Computer memory / Electronic engineering


An FPGA architecture for DRAM-based systolic computations Norman Margolus Boston University Center for Computational Science and MIT Artificial Intelligence Laboratory Abstract
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Document Date: 2005-01-16 13:05:57


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City

Yorktown / San Diego / /

Company

IBM / RAMBUS / MIT Press / IEEE Comp / MIT AI Laboratory / /

Currency

AMD / /

Facility

University Center / University ECSE Dept. / /

IndustryTerm

volume image processing / physical processor / lattice-gas simulations / lattice gas crystallizing / simulated tracer-gas / virtual processing scheme / oil / circuitry on-chip / offchip / logic-synthesis tools / systolic applications / mesh algorithms / virtual processor / graphical applications / sync-burst chip / image processing / neural-networks / 3D physical systems / physical processing nodes / microprocessor chip / insurance against bugs in complex processor / memory technology / 3D systems / porous media / memory chips / physical systems / machine processing node / Table lookup algorithms / physical processors / virtual-processor / lattice-gas liquid / /

NaturalFeature

RAMBUS channel / /

Organization

National Science Foundation / Boston University Center for Computational Science / MIT / MIT Lab. for Computer Science / Data / ASIC / American Mathematical Society / Boston University / /

Person

Y. Rabin / N. Margolus / Latanya Sweeney / T. Toffoli / Tom Knight / Stanford Ph / Norman Margolus / /

Position

dedicated DRAM controller / DRAM-I/O controller / controller / and burst buffers / DRAM I/O controller / DRAM controller / /

ProvinceOrState

California / /

Technology

two memory chips / FPGA / FPGA chip / proposed chip / 1 Processor / Table lookup algorithms / proposed FPGA chip / SRAM / image processing / 3 Processor / MRI / memory technology / 128 DRAM chips / 2 Processor / ASIC / mesh algorithms / sync-burst chip / artificial intelligence / reconfigurable FPGA-like processors / return wavefront Processor / microprocessor chip / how four processors / crystallization / virtual processor / physical processor / simulation / FPGA circuitry on-chip / DRAM chips / DSP / DRAM chip / Parallel Processing / CA algorithms / FPGA chips / using a synchronous-burst FPGA / /

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