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IEEE standards / Computing / Field-programmable gate array / Joint Test Action Group / Xilinx / Backplane / Electronic engineering / Electronics / Computer buses


From SP02 to SP04 Lev Uvarov UF Muon Trigger Meeting January 8, 2004
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Document Date: 2004-02-04 09:07:42


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File Size: 42,61 KB

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Company

Xilinx / /

Facility

University of Florida SP02 Fixes / University of Florida / /

Organization

University of Florida SP02 Latency Budget SPO2 Simulated Timing From Muon Port Card Latency TLK2501 Deserializer Front FPGA / University of Florida / /

Person

Lev Uvarov / /

ProvinceOrState

Mississippi / Florida / /

Technology

four chips / FPGA / 5 Sector Processor / JTAG / /

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