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DARCO: Infrastructure for Research on HW/SW co-designed Virtual Machines Demos Pavlou‡,1, Aleksandar Brankovic, Kyriakos Stavrou, Enric Gibert,
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Document Date: 1980-01-01 01:00:00

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File Size: 1,35 MB

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City

Boston / /

Company

IBM / Software Dynamic Translation Systems / HW/SW W/SW co / Main co / Intel Corporation / Software co / Addison Wesley Longman Publishing Co. Inc. / DARCO / Code Morphing Software / Standard Performance Evaluation Corporation / Microsoft / Intel Labs / /

Country

United States / /

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Facility

Y Interpret Store / Code$ Store / /

IndustryTerm

appropriate tools / generation algorithm / host processor / integer applications / allocation algorithm / crusoe processors / conventional list scheduling algorithm / incomplete tools / short applications / reconfigura-ble software / off-the-critical path hardware / x86 applications / search enabler / software layer / mature and debugged tool / specific hardware / software layers / in-order processor / /

OperatingSystem

VMs / /

Organization

‡Intel Barcelona Research Center / Maria Gregori Antonio Gonzalez† / ‡ †Universitat Politécnica de Catalunya / Spanish Ministry of Education / Universitat Politecnica de Catalunya / Committee on Computer Architecture Newsletter / US Federal Reserve / /

Person

Rakesh Kumar / Aleksandar Brankovic / Demos Pavlou / Pass Backward / Maria Gregori Antonio Gonzalez / /

Position

branch The translator / translator / ESL Int FP Averages Averages Interpreter Overhead BB Translator Overhead SB Translator / translator / a scheduler / interpreter / a translator / dynamic translator / interpreter / Research assistant / instruction scheduler / static basic blocks Interpreter / Interp$ Chain SSA Forward / Controller Controller / representative / QEMU translator / Controller / /

Product

a full-system x86 / CPU 2006 / x86 / /

ProgrammingLanguage

Java / FP / /

PublishedMedium

IEEE Transactions on Computers / Microprocessor Report / /

Technology

Virtual Machine / crusoe processors / Crusoe / operating system / in-order processor / host processor / BBs / PPC processor / PowerPC processor / Java / SB generation algorithm / conventional list scheduling algorithm / simulation / allocation algorithm / /

URL

http /

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