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Switches / Digital circuits / Operations research / Planning / Scheduling / Arbiter / Crossbar switch / Priority encoder / Decoder / Electronic engineering / Electrical engineering / Electronics


VLSI Micro-Architectures for High-Radix Crossbar Schedulers Giorgos Passas Manolis Katevenis
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Document Date: 2014-02-26 11:54:10

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City

Pittsburgh / /

Company

FARADAY Technology Corporation / Parallel & Distributed Systems / /

Country

United States / /

Currency

USD / /

/

Facility

High-Radix Crossbar Schedulers Giorgos Passas Manolis Katevenis Dionisios Pnevmatikatos Institute of Computer Science / Technical University of Crete / University of Crete / /

IndustryTerm

metal tracks2 / metal tracks / mechanism to resolve protocol / metal layers / on-chip inteconnection networks / radix router / parallel prefix networks / iSLIP scheduling algorithm / local-area networks / router chips / interconnection networks / metal-track area / metal track / energy efficiency / 8logN metal tracks / iSLIP algorithm / switch chip / /

Organization

Computer Engineering / Microprocessor & Hardware Lab. / High-Radix Crossbar Schedulers Giorgos Passas Manolis Katevenis Dionisios Pnevmatikatos Institute of Computer Science / Computer Science Department / University of Crete / European Commission / Foundation for Research and Technology / Department of Electronic & Computer Engineering / International Criminal Court / /

Person

Micro / /

Position

cross iSLIP scheduler / iSLIP arbiter / speed-optimized arbiter / FIFO Scheduler / iSLIP scheduler / General / block FIFO scheduler / area-optimized arbiter / arbiter / output arbiter / block iSLIP scheduler / cross VC scheduler / Wavefront Scheduler / round-robin arbiter / input arbiter / grant output arbiter / second-level arbiter / output arbiter / for the OR / crossbar scheduler / scheduler / speed-optimized iSLIP scheduler / VC Scheduler / cross FIFO scheduler / block VC scheduler / leftmost output arbiter and the bottom input arbiter / Arbiter Area An arbiter / input and output arbiter / /

ProvinceOrState

Oregon / /

PublishedMedium

IEEE Transactions on Computers / /

Technology

FPGA / router chips / p2p / high-radix router / SRAM / iSLIP algorithm / 90nm CMOS technology / flow control / simulation / switch chip / iSLIP scheduling algorithm / 2.1 The iSLIP Algorithm The iSLIP algorithm / /

URL

www.faraday-tech.com / /

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