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VHDL / Verilog / IEEE / Hardware description languages / Electronic engineering / Digital electronics


VSI AllianceTM Soft and Hard VC Structural, Performance and Physical Modeling SpecificationVersion 2.1 (I/V 1 2.1)
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Document Date: 2008-07-19 13:20:44

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File Size: 150,55 KB

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City

Leeds / /

Company

Fujitsu / Toshiba / LSI Logic / Synopsys / Mentor Graphics / Cypress Semiconductor / Cadence Design Systems / Design Constraints Working Group / RTL / Alliance Specification (I/V 1 2.1) Implementation/Verification Development Working Group / OVI Design Constraints Working Group / Development Working Group / Sente Technical / /

Facility

Open Library / /

IndustryTerm

copyright law / /

Organization

VSI Alliance / Public Domain VSI Alliance / /

Person

Jerry Frenkil / John Biggs / Mitch Heins / Andres Teene / Mike Andrews / Wilsa Schroers iii / Michael Berend / Daniel Ryan / Mark Hahn / Cedric Iwashina / Karen Bartleson / Jin-Sheng Shyr / /

Position

Editor / Co-Chair / Chair / /

ProgrammingLanguage

Verilog / /

Technology

Verilog / API / integrated circuits / VHDL / /

URL

http /

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