<--- Back to Details
First PageDocument Content
Application programming interfaces / Computer architecture / Message Passing Interface / Graphics hardware / Multi-core processor / Coprocessor / Embedded system / Computer cluster / Hardware acceleration / Computing / Parallel computing / Central processing unit
Date: 2013-07-28 00:11:23
Application programming interfaces
Computer architecture
Message Passing Interface
Graphics hardware
Multi-core processor
Coprocessor
Embedded system
Computer cluster
Hardware acceleration
Computing
Parallel computing
Central processing unit

Programming the Nallatech Xeon + Multi-FPGA Platform

Add to Reading List

Source URL: www.hotchips.org

Download Document from Source Website

File Size: 406,52 KB

Share Document on Facebook

Similar Documents

Project Profile EMPHYSIS Enhanced production code for improved system performance The major goal of the ITEA project EMPHYSIS (EMbedded systems with PHYSical models In the production code Software) is to enhance the pro

DocID: 1vpDT - View Document

Robust, low-cost, auditable random number generation for embedded system security Ben Lampert?◦ Riad S. Wahby? ?

DocID: 1vfw4 - View Document

Mining Task Precedence Graphs from Real-Time Embedded System Traces Oleg Iegorov Sebastian Fischmeister

DocID: 1uWNC - View Document

Flash File System Considerations Charles ManningWe have been developing flash file system for embedded systems sinceDuring that time, we have gained a wealth of knowledge and experience. This document

DocID: 1uCcP - View Document

Algorithms for Optimal Power Allocation of Wireless Multi-Hop Heterogeneous Networks under Statistical Delay Constraints Neda Petreska (joint work with J. Gross and H. Al-Zubaidy) Fraunhofer Institute for Embedded System

DocID: 1uAOI - View Document