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Cache / Central processing unit / Computer architecture / CPU cache / Hardware performance counter / Memory hierarchy / Cache algorithms / Cache-oblivious algorithm / Computer hardware / Computer memory / Computing


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Document Date: 2004-06-29 10:13:46

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File Size: 1,31 MB

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Company

AT&T / /

Currency

USD / /

IndustryTerm

applications software / into production systems / invalidation cache coherence protocol / applications using hardware / counter hardware / compiler tool / software tools / naive algorithm / Update software / hardware devices / performance tuning device / hardware event tracing systems / proposed counting hardware / inner loop product / per-processor / appropriate software tools / library hardware / th~ naive matrix multiplication algorithm / coherence protocol / actual applications / hardware tracing systems / software counter / /

OperatingSystem

GNU / PIOS / /

Organization

Pr0ces40r Unit / /

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Position

advocate / cache controller / driver / meaningful programmer / Cray X-MP / rt / simple / automatic device driver / device driver / problems driver / external cache controller / interpreter / programmer / /

ProgrammingLanguage

Fortran / C / /

Technology

SuperSparc processor / th~ naive matrix multiplication algorithm / 4 processors / flow control / 20 processor / Examining algorithm / invalidation cache coherence protocol / coherence protocol / cache memory / 6 processor / naive algorithm / simulation / operating system / 6-wa~ algorithm / specific processor / packet-switched / /

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