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Computer engineering / Instruction set / Microarchitecture / CPU cache / Program counter / MIPS architecture / Central processing unit / Computer hardware / Computer architecture


Microsoft PowerPoint - HC18.720.S7T2.A Novel Processor Architecture for High-Performance Stream Processing.ppt
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Document Date: 2013-07-27 23:56:09


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IBM Zurich Research Laboratory / IBM Corporation / Zurich Research Laboratory / /

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programmable state machine technology / conventional processors / instruction / parallel processing / search algorithm / real-time evaluation / search engines / /

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Zurich Research Laboratory High-Level Concept / R1 / Zurich Research Laboratory Programmable State Machine / /

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encryption / 4 Hot Chips / 7 Hot Chips / 9 Hot Chips / HW engine Hot Chips / 5 Hot Chips / 3 Hot Chips / 8 Hot Chips / van Lunteren Hot Chips / BaRT search algorithm / Summary 2 Hot Chips / programmable state machine technology / parallel processing / High-Level Concept Conventional processor / 6 Hot Chips / /

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