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Dataflow Architectures for 10Gbps Line-rate Key-value-Stores Michaela Blott, Kees Vissers - Xilinx Research © Copyright 2013 Xilinx .
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Document Date: 2013-08-16 18:30:06

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File Size: 2,25 MB

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City

New York / /

Company

Typical Implementations Hardware / Intel / Xilinx / /

Country

United States / /

Currency

AMD / /

Facility

store areas/items Page / L3 Cache Threads stall / Value Store / /

IndustryTerm

Web server Web server Web server Memcached Memcached Memcached server / network processing / databases Web server Web server Web server / /

OperatingSystem

L3 / /

Person

Michaela Blott / David Meisner / Ali G. Saidi / Parthasarathy Ranganathan / Kees Vissers / Thomas F. Wenisch / Kevin Lim / /

Position

Memory allocation* General / meta-data Hash Table Value Store DRAM Controller / /

ProvinceOrState

Nova Scotia / New York / /

Technology

FPGA / Ethernet / Data caching / UDP / TCP/IP / Parallel Processing / Web server / /

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