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Computing / Electronics / Video cards / Error detection and correction / Coding theory / Low-density parity-check code / Error floor / CUDA / Graphics processing unit / GPGPU / Computer hardware / Graphics hardware


High Throughput Low Latency LDPC Decoding on GPU for ...SDR Systems Guohui Wang, Michael Wu, Bei Yin, and Joseph R. Cavallaro Department of Electrical and Computer Engineering, Rice University, Houston, TexasEmail
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Document Date: 2013-09-15 02:28:52


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File Size: 1,29 MB

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City

Austin / /

Company

Texas Instruments / NVIDIA / GPU / Xilinx / Intel / /

Country

United States / /

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Facility

store Rmn / Rice University / Store dR / /

IndustryTerm

storage applications / forwardbackward algorithm / runtime management / forward-backward algorithm / depth-first scheduling algorithm / node processing / Wireless Commun / tag-based parallel early termination algorithm / kernel processing time / sign product / host→device / check node processing / multi-codeword decoding algorithm / sum-product algorithm / stream multi-processors / wireless communication / /

NaturalFeature

GPU streams / /

OperatingSystem

Linux / /

Organization

Rice University / Houston / US National Science Foundation / Joseph R. Cavallaro Department of Electrical and Computer Engineering / International Criminal Court / /

Person

Michael Wu / G. Falcão / V / Joseph R. Cavallaro / Min-Sum Algorithm / J. Andrade / V / Bei Yin / /

Product

Stream / CPU / /

ProgrammingLanguage

L / FP / C / /

ProvinceOrState

Texas / /

Technology

stream multi-processors / sum-product algorithm / tag-based parallel early termination algorithm / Linux / two-min algorithm / Min-Sum algorithm / http / forwardbackward algorithm / simulation / two-min decoding algorithm / shared memory / Application Specific Processors / MSA algorithms / multi-codeword decoding algorithm / forward-backward algorithm / two algorithms / /

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