| Document Date: 2013-10-17 13:27:38
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Company IBM / Lincoln Laboratory / LINCOLN LABORATORY JOURNAL / Vertex / Intel / / IndustryTerm conventional processing / government applications / digital signal processor / packet-routing network / sparse matrix processing / individual node processor / partial product / transportation / graph algorithm applications / conventional parallel processors / Graph processing computational throughput / social networking patterns / promising new processor / important benchmark graph algorithms / localized processing / graph processing / Internet data / conventional communication network / control processor / scientific computing applications / conventional multicore processors / 3D communications / large message-based communications / graph algorithms / conventional processor / electromagnetic coupling communications / identical processors / partial products / transaction processing / large database applications / node processors / conventional processors / graph processor / statistical routing algorithm / electricity / software development efficiency / interprocessor communications / dense matrix processing / parallel graph processor / plate 3D processor chassis 3D parallel processor / node processor / 3D graph processor / large graph processing / conventional general-purpose processor / computation hardware / processor network / large conventional computing tasks / 3D toroidal communication network / sparse matrix processors / 2D communications / large matrices over many processor / communications module / identical network / social networks / low-power communication network / test chips / matrix algorithms / communication network / Parallel processors / message-routing algorithms / parallel processor / sort algorithm / / Organization IL RB / / Person William S. Song / Huy T. Nguyen / JOSHUA I. KRAMER / Vitaliy Gleyzer / T. NGUYEN / Jeremy Kepner / / Position matrix writer / throughput driver for many important benchmark graph algorithms / node controller / conductor / writer / analyst / controller / / ProvinceOrState Texas / / Technology Joshua I. Kramer Graph algorithms / processor chassis 3D parallel processor Routing layer Processor / graph processor / high-speed / low-power Coupling connector Insulator TX/RX Coupler TX/RX Stacked processor / sparse matrix processors / Sparse Matrix Algebra-Based Processor / 3D graph processor / parallel processor / Parallel Graph Processor / statistical routing algorithm / conventional parallel processors / Multicore processors / SRAM / Cold plate 3D processor chassis 3D parallel processor / Nonvolatile memory / implementing graph algorithms / process control / digital signal processor / embedding graph algorithms / graph algorithms / sort algorithm / node processors / Flash memory / conventional processor / sparse matrix algorithms / important benchmark graph algorithms / individual node processor / Zeon processors / control processor / control processor Node processor Node processor / simulation / Node processor / conventional multicore processors / test chips / message-routing algorithms / 1024-node processor / 106 106 1 10 100 1000 Processors / /
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NOVEL GRAPH PROCESSOR ARCHITECTURE Novel Graph Processor Architecture William S. Song, Jeremy Kepner, Vitaliy Gleyzer, Huy T. Nguyen, and Joshua I. Kramer