CHERI ISA / Memory-Management Unit / CHERI CPU / Memorial University / University College London / CPU MMU / University of Cambridge / /
Person
Compartment / Michael Roe / Jonathan Anderson / Nirav Dave / Peter G. Neumann / Steven J. Murdoch / David Chisnall / CHERI FPGA / Stacey Son / HERI BSD KERNEL / Memory Fig / Jonathan Woodruff / Robert Norton / Ben Laurie / Robert N. M. Watson / Brooks Davis / Kernel Capsicum / ASE S TUDIES CHERI / Simon W. Moore / /
Position
lightweight object-capability model for application compartmentalization / supervisor / address-space executive / executive / programmer / process model / TLB $idc $pcc Data Cache L2 Cache $idc $pcc Tag Controller / userspace address-space executive / objectcapability model / model / software supervisor / memory-management and capability executive / /