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CPU cache / Cache / Central processing unit / Computer memory / Multi-core processor / Intel Core / Parallel computing / Power supply / Scheduling / Electronic engineering / Computing / Electronics


1702 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 12, DECEMBER 1999 Power Optimization of Variable-Voltage Core-Based Systems
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Document Date: 2003-06-11 14:31:52

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File Size: 283,00 KB

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City

Mountain View / /

Company

Fujitsu / DESIGN METHODOLOGY FOR VARIABLE-VOLTAGE SYSTEMS / Princeton / VARIABLE-VOLTAGE CORE-BASED SYSTEMS / Synopsys Inc. / Independent JPEG Group / Suzuki / D. Variable-Voltage Hardware / Intel / /

Country

United States / /

Currency

USD / /

Event

Reorganization / /

Facility

Stanford University / University of California / Massachusetts Institute of Technology / /

IndustryTerm

semiconductor technology / static scheduling algorithms / wireless communications applications / multimedia server / variablevoltage scheduling algorithm / low-power software / design space using search algorithms / static nonpreemptive software scheduling algorithm / reactive hard real-time systems / search technique / communication protocol / supply-voltage chips / synthesis algorithms / programmable processors / bound algorithm / real-time constraints / energy / target applications / it possible to create processor / real-time scheduling algorithm / embedded control applications / energy dissipation / average energy / preemptive scheduling algorithm / nonpreemptive scheduling solutions / evaluated cache systems / application-specific systems / higher energy efficiency / energy efficiency / actual applications / decompression utilities / variable voltage hardware / variable voltage systems / battery technology / preemptive static scheduling algorithm / application-driven search / voltage systems / real-time systems / nonpreemptive scheduling algorithm / compression algorithm / software programmable processor / realtime systems / search process / embedded systems / hardware/software / low-power core-based system-on-a-chip / fixed voltage processor / uniprocessor systems / final solution / personal computing / search strategy / signal processing / communication applications / event-driven systems / software scheduling / cache delay estimation tool / search algorithm / minimum energy schedule / technology level / system energy consumption / implementation technology / portable systems / optimization algorithms / software implementation / forward error corrector chip / nonpreemptive scheduling solution / energy-efficient system configuration / synthesis search loop / communication devices / resource allocation algorithm / energy dissipation improvement / zero-energy consumption / low-power hardware / nominal energy consumption / variablevoltage systems / energy model / digital signal processing / task-scheduling algorithm / /

Organization

Massachusetts Institute of Technology / U.S. Securities and Exchange Commission / Computer Science Department / Department of Electrical Engineering / Stanford University / University of California / Los Angeles / /

Person

Darko Kirovski / Miodrag Potkonjak / Ratio Cache Miss Penalty Cache / Inki Hong / Gang Qu / E. Macii / /

Position

author / variable-voltage task scheduler / Editor / tasklevel scheduler / preemptive scheduler / scheduler / /

ProgrammingLanguage

C / /

ProvinceOrState

Utah / California / Massachusetts / /

PublishedMedium

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS / /

SportsLeague

Stanford University / /

Technology

forward error corrector chip / image compression / synthesis algorithms / preemptive scheduling algorithm / 3-D / search algorithm / X terminal / implementation technology / SRAM / INTEGRATED CIRCUITS / CMOS chips / real-time scheduling algorithm / task-scheduling algorithm / resource allocation algorithm / compression algorithm / optimization algorithms / communication protocol / static scheduling algorithms / fixed voltage processor / GSM / design space using search algorithms / semiconductor / JPEG / semiconductor technology / wireless communications / variablevoltage scheduling algorithm / static nonpreemptive software scheduling algorithm / system-on-a-chip / DSP processor / preemptive static scheduling algorithm / CMOS technology / VLSI chips / RISC processor / battery technology / nonpreemptive scheduling algorithm / simulation / DSP / software programmable processor / evaluated using tracedriven simulation / /

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http /

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