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Logic design / Fabless semiconductor companies / Integrated circuits / Field-programmable gate array / Reconfigurable computing / Xilinx / Altera / Application-specific integrated circuit / Placement / Electronic engineering / Digital electronics / Electronic design automation


IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 2, FEBRUARY[removed]
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Document Date: 2012-09-19 11:13:08

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File Size: 259,15 KB

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City

Madrid / /

Company

VCCINT / Synopsys / Altera / RTL / IEEE Authorized / TSMC / STMicroelectronics / Authorized / Xilinx / CMC Microsystems / /

Country

Canada / /

Currency

USD / /

/

Facility

building ASICs / University of Toronto / /

IndustryTerm

placement tool / power estimation tools / energy-consumption gap / post-manufacturing tests / image processing / v5.0SP1 software / synthesis tool / prefabricated media / manufacturing / clock networks / implementation media / metal fill / /

Organization

FPGA / ASIC / Department of Electrical and Computer Engineering / University of Toronto / Toronto / Natural Sciences and Engineering Research Council of Canada / /

Person

Ian Kuon / Jonathan Rose / A. DeHon / /

Position

Editor / system architect / designer / /

Product

II v5.0SP1 software / LogicLock / II v5.0SP1 / /

ProgrammingLanguage

Verilog / C / /

PublishedMedium

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS / /

Technology

ethernet / FPGA / ASIC / Verilog / GPS / two technologies / simulation / SRAM / 90-nm CMOS technology / image processing / Digital Object Identifier / DSP / 0.15-µm CMOS technology / VHDL / INTEGRATED CIRCUITS / CMP / CAD / /

URL

http /

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