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Embedded systems / Debugging / IEEE standards / Microcontrollers / In-circuit emulator / Field-programmable gate array / System on a chip / Joint Test Action Group / Emulator / Electronics / Electronic engineering / Computing


Common and Key Technologies Supporting Advanced Products Processor Design Verification Using the Hybrid Emulator YAMADA Kazuo, NISHIMOTO Hiroaki, DAITO Masayuki, ONO Hirohiko Abstract
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Document Date: 2013-10-01 21:36:42

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File Size: 1,07 MB

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Company

NEC Electronics Corporation / Systems Ltd. / Software Co / LSI / NEC’s System IP Core Research Laboratories / SW Development Resources / Processor Performance Benchmarks / /

IndustryTerm

system-on-chip / individual products / Processor product / microcomputer product / fabricated actual chip / car-mount use / actual chip / sample chip / /

Organization

Hybrid Board / Microcomputer Operations Unit / NEC’s System IP Core Research Lab / Technology Foundation Development Operations Unit / /

Person

Ko Yoshikawa / Takeshi Yoshimura / Ichiro Kuroda / Yuichi Nakamura / Kouhei Hosokawa / /

Position

NISHIMOTO Hiroaki Assistant Manager / 2nd System-on-a-Chip Design Division / ONO Hirohiko Group Manager / Microcomputer Software Division / Electronic Devices DAITO Masayuki Department Manager / 1st Microcomputer Division / Manager / 1st Microcomputer Division / Manager / Design Engineering Development Division / Manager / Microcomputer Software Division / Assistant Manager / 2nd System-on-a-Chip Design Division / /

ProgrammingLanguage

C / C++ / /

PublishedMedium

the NEXUS / /

Technology

Design Verification / FPGA / CPU debugging protocols / system-on-chip / actual chip / JTAG / sample chip / 6 Processor / System-on-a-Chip / previous processors / fabricated actual chip / GUI / 5 Protocol / /

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