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Fast and Cycle-Accurate Modeling of a Multicore Processor Asif Khan, Muralidaran Vijayaraghavan, Silas Boyd-Wickizer and Arvind Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technolog
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Document Date: 2013-05-07 10:49:08

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Washington / DC / Vancouver / /

Company

IBM / FPGA-Accelerated Simulation Technologies / IEEE Computer / A-Port Networks / Modeling Networked Systems / J. Kim N. A. / IEEE Press / AMD / RTL / H. Angepat N. A. / Xilinx / Quanta Computer / /

Country

United States / Canada / /

Currency

AMD / USD / /

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Event

Company Expansion / /

Facility

port Arete / Pthreads library / Artificial Intelligence Laboratory Massachusetts Institute of Technology / PowerPC pipeline / parallelized using the Pthreads library / /

IndustryTerm

on-chip network / on software simulators / cache-coherence protocol / deadlock-free network / software side / dataflow networks / topologies as well as routing algorithms / large multicore systems / out-of-order superscalar processors / hardware-software partitioning / out-of-order processors / software handles / processor chip / software management / onchip network / out-of-order processor / software simulators / software-based multicore simulators / simulation infrastructure / multicore processor / /

MarketIndex

PARSEC / /

OperatingSystem

UNIX / Linux / /

Organization

Massachusetts Institute of Technology / IEEE Computer Society / Swiss Army / /

Person

K. E. Moore / Kattamuri Ekanadham / Silas Boyd-Wickizer / Jessica Tseng / C. J. Hughes / V / /

Position

network controller / PowerPC Core L2 Cache Directory Controller Network Layer Peripherals / architect / thread stealing scheduler / memory controller / Multifacets General / /

Product

Arete / Bluespec System Verilog / BDN / /

ProgrammingLanguage

C / Python / Verilog / DC / C++ / /

PublishedMedium

Linux Journal / /

Technology

FPGA / MSI protocol / FPGA chip / RAM / multicore processor / cache-coherence protocol / UNIX / Linux / out-of-order processors / distributed protocol / processor chip / operating system / shared memory / Operating Systems / out-of-order superscalar processors / VHDL / A. Processor Architecture The processor / time-division multiplexing / one FPGA chip / Verilog / out-of-order processor / flow control / System-on-Chip / simulation / DSP / /

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