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Central processing unit / Instruction set architectures / Microprocessors / MIPS architecture / CPU cache / Microarchitecture / Classic RISC pipeline / Computer architecture / Computer hardware / Computer engineering


™ The SB-1 Core: TM A High Performance,
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Document Date: 2013-07-27 23:38:17

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File Size: 154,50 KB

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Company

Integrated SOC Solutions / TM MIPS64 Implementation David Kruckemyer Principal / /

Facility

Store Unit / Issue stalls / stalls Fetch1 Fetch2 Decode Issue S1 S2 S3 S4 Decode/Issue / Eliminates pipeline / /

IndustryTerm

embedded networking / /

Organization

MADD / SB-1 Load/Store Unit / Branch Evaluate Unit / SB-1 Integer Unit / Integer Multiply/Divide Unit / /

Person

Coherency / /

Position

High Level Spec ISA Frequency Microarchitecture Branch Prediction Instruction Cache Data Cache TLB MP / Full MP / Engineer / /

ProgrammingLanguage

FP / /

Technology

1GHz ~25mm2 Hot Chips / 15/2000 Hot Chips / CMP / /

URL

www.sibyte.com / /

SocialTag