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Central processing unit / Compiler optimizations / Instruction set architectures / Classes of computers / Software pipelining / Instruction pipeline / MIPS architecture / Reduced instruction set computing / Transport triggered architecture / Computer architecture / Computer engineering / Computer hardware


An Overview of Static Pipelining Ian Finlaysony , Gang-Ryung Uhz , David Whalleyy and Gary Tysony y Department of Computer Science z Department of Computer Science
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Document Date: 2011-08-10 14:26:43


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Washington / DC / Braga / Austin / /

Company

RTL / Signal Processing Systems / Cambridge Univ Press / /

Country

United States / Portugal / /

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Facility

VPO MIPS port / MIPS port / C library / /

IndustryTerm

software pipelining / energy efficient features / processor energy / lower energy cost / energy consumption / reduced energy consumption / software-pipelining / energy inefficiencies / energy-efficient manner / energy consumption values / processor energy consumption / mobile devices / simpler hardware / power electronics / conventional processor / energy reduction / register file energy consumption / overlapped using software pipelining / /

MarketIndex

VALUATION / /

OperatingSystem

GNU / /

Organization

vol. / National Science Foundation / Department of Computer Science / Boise State University / Florida State University / Cambridge Philosophical Society / IEEE Computer Society / /

Person

Embedded Benchmark / Gang-Ryung Uhz / Pipelining Ian Finlaysony / David Whalleyy / Gary Tysony / /

Position

Representative / WB / MEM WB / /

ProgrammingLanguage

DC / C / /

Technology

conventional processor / DSP / Digital Signal Processors / two-stage processor / mobile devices / /

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