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Hardware description languages / Hardware verification languages / Logic design / Technical communication / Verilator / Verilog / High-level synthesis / VHDL / Logic simulation / Electronic engineering / Digital electronics / Electronic design automation


Appears in the Proceedings of the 47th Int’l Symp. on Microarchitecture (MICRO-47), December[removed]PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research Derek Lockhart, Gary Zibrat, and Ch
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Document Date: 2015-03-29 23:28:17

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File Size: 838,62 KB

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Company

PyMTL / Synopsys / RTL / /

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Facility

Port Interfaces Modeling Tools Third-party Algorithm Packages / Building RTL / Python Standard Library / Cornell University / PyMTL library / /

IndustryTerm

simulator software / on-chip network / visualization tools / specialization machinery / translation tool / energy constraints / energy metrics / dot product operator / energy goals / publicly-available research tools / energy / metal / scientific computing community / classic object-oriented software / clean boundary between hardware / mesh network / technology scaling / communication protocols / dot product algorithm / software architecture / /

Organization

Cornell University / Christopher Batten School of Electrical and Computer Engineering / ASIC / /

Person

Ai / Mux ( nbits ) s.connect / Register / Derek Lockhart / Gary Zibrat / /

Position

model for final system-level integration testing / translator / VCD Translator / interpreter / offthe-shelf Python interpreter / Model / designer / golden model for validating more detailed implementations / /

Product

CL / /

ProgrammingLanguage

FL / MATLAB / C / Python / CPython / Verilog / C++ / /

ProvinceOrState

Florida / /

Technology

FPGA / dot product algorithm / VHDL / ASIC / Verilog / flow control / RISC processor / Latency-insensitive protocols / caching / simulation / communication protocols / /

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