National Park Service / 80C186XL CORE ARCHITECTURE 80C186XL Clock Generator Bus Interface Unit / Refresh Control Unit / /
Person
Cycle Timings / Crystal Inputs / /
Position
bus controller / local bus controller / local bus The bus controller / Controller / Select Logic Programmable Wait State Generator Local Bus Controller / /
ProgrammingLanguage
RC / R / DC / /
RadioStation
CORE / /
Technology
one chip / RAM / required processor / memory chip / clock The processor / 68-Pin Plastic Leaded Chip / properly programmed chip / fourth chip / seven peripheral devices These chip / ALE / HOLD HLDA protocol / 6 memory chip / /