The Proposed Level-3 Trigger System for STAR C. Adler a , J. Berger a , M. Demello b , D. Flierl a , J. Landgraf c , J. S. Lange a; 1 , M. J. LeVine c , V. Lindenstruth d , A. Ljubicic,Jr. c , J. Nelson e , D. Roehrich f

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Date: 2002-06-20 11:42:50 Instruction set architectures Computer memory Motherboard Intel i960 Microcontrollers Classes of computers DEC Alpha CPU cache Reduced instruction set computing Computer hardware Computer architecture Computing		The Proposed Level-3 Trigger System for STAR C. Adler a , J. Berger a , M. Demello b , D. Flierl a , J. Landgraf c , J. S. Lange a; 1 , M. J. LeVine c , V. Lindenstruth d , A. Ljubicic,Jr. c , J. Nelson e , D. Roehrich f Add to Reading List Source URL: www.star.bnl.gov Download Document from Source Website File Size: 172,74 KB Share Document on Facebook

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