| Document Date: 2003-04-01 22:10:24
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Company IBM / Rambus / Intel / / Facility ReEnact library / Josep Torrellas University of Illinois / / IndustryTerm them in hardware / software failures / registers/processor / software data structures / 256K 130x130 car / software releases / software problems / software reliability / software bugs / user site / software / software tools / detection tool / software instrumentation / real time / out-of-order superscalar processors / software debugging / speculative epochs per processor / on-chip 4X4 crossbar network / software intervention / coherence protocol / debugging hardware / cache coherence protocol / / Organization University of Illinois / National Science Foundation / / Person Ray Trace / Epoch Footprint (Kbytes) / App / Maximum Epoch Footprint (Kbytes) / Milos Prvulovic / / Position memory RT / RT / skilled programmer / producer / programmer / head / / Product ReEnact / SPLASH-2 applications / SPLASH-2 / / ProgrammingLanguage FP / / ProvinceOrState Illinois / / Technology Alpha / 4 processors / four processors / TLS protocol / coherence protocol / cache coherence protocol / MESI protocol / 79 ns ReEnact Parameters Threads/processor / out-of-order superscalar processors / / URL http /
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Appears in the Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA-30), June[removed]ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes Milos Prv