| Document Date: 2014-06-24 17:54:38
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Company Row Bank / Intel Labs / AMD / 3M / Column Bank Refresh / / Currency USD / AMD / / Event Product Issues / / Facility Carnegie Mellon University / Sandy Bridge / Ivy Bridge / / IndustryTerm low-overhead solution / secure computing system / energy-efficiency / process technology / desired bank / bank / hot-carrier injection / bank address / software pages / potential solutions / actual chip manufacturer / possible solutions / out-of-order processors / technology node / process technology scales / exhaustive search / consumer-grade systems / / OperatingSystem PREX / / Organization High-Level Organization / Carnegie Mellon University / DRAM / / Person Konrad Lai Onur / Chris Fallin Ji Hye / Ross Daly Jeremie / / Position Colonel / Major / Memory controller / controller / The memory controller / external temperature controller / / Product PCIe / 2GB DDR3 module / B52 / Code 1a / 2GB DDR3 / row / addresses / / ProvinceOrState Rhode Island / / Technology cells Processor / High-Level Organization data cmd addr MemCtrl DRAM chips / FPGA / 8 chips / seven chips / 836 chips / commodity DRAM chips / four processors / artificial intelligence / re-mapped chip / extra DRAM chips / individual DRAM chip / out-of-order processors / 972 DRAM chips / erroneous DRAM chips / DRAM chips / process technology / DRAM chip / Timing Organization Chip / DRAM process technology / /
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Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors Yoongu Kim1 Ross Daly Jeremie Kim1 Chris Fallin Ji Hye Lee1 Donghyuk Lee1 Chris Wilkerson2 Konrad Lai Onur Mutlu1 1