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Cache coherence / Cache / CPU cache / Parallel computing / Computing / Cache coherency / Computer hardware


Automatic Generation of Veri able Cache Coherence Simulation Models from High-level Speci cations A.J. Field, P.G. Harrison, K. Kanani fajf,pgh, Department of Computing Imperial College
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Document Date: 2011-11-14 07:17:02

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City

READING / London / /

Company

Spade SPA / BUSSNP / /

Country

United Kingdom / /

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Event

FDA Phase / /

Facility

Computing Imperial College / Spade SPA / /

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IndustryTerm

coherency protocols / cache coherency protocol / closed systems / write-through coherency protocol / cache coherency protocols / actual coherency protocol / partial systems / multi-processor systems / coherency protocol / /

Organization

Organization of a Spade / Organisation of Spade / /

Position

designer / workload model for the protocol / /

Product

CACHE agent / CPU / cache / READING / WRITING / /

ProgrammingLanguage

C / C++ / /

Technology

actual coherency protocol / cache coherency protocol / write-through coherency protocol / coherency protocols / cache coherency protocols / Caching / Simulation / sequential consistency / shared memory / coherency protocol / /

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