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Electronics / Finite-state machine / State transition system / Verilog / Transition / Token ring / Timer / Specification and Description Language / Models of computation / Electronic engineering / Computing


IF: An Intermediate Representation for SDL and its Applications Marius Bozga , Jean-Claude Fernandez , Lucian Ghirvu  , Susanne Graf , Jean-Pierre Krimm , Laurent Mounier and Joseph Sifakis VERIMAG, Centre Equation, 2 a
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Document Date: 2012-12-31 04:25:31


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Company

Cnet / Sema Group / BP / /

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IndustryTerm

leader election algorithm / validation tools / sdl systems / labeled transition systems / possible solutions / erent validation tools / telecommunication systems / erent tools / circular network / distributed timed systems / /

Organization

Centre Equation / United Nations / /

Person

Jean-Claude Fernandez / Susanne Graf / Marius Bozga / Joseph Sifakis / Laurent Mounier / Jean-Pierre Krimm / /

Position

DISTRIBUTED LEADER / guard / translator / /

Technology

token ring / analysis algorithms / simulation / Verilog / leader election algorithm / existing technology / be done using a leader election algorithm / /

URL

http /

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