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Electronic engineering / Field-programmable gate array / Advanced Encryption Standard / Xilinx / Data Encryption Standard / Block cipher / Lookup table / Cryptography / Computing / Reconfigurable computing


Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES Ga¨el Rouvroy, Fran¸cois-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
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Document Date: 2007-11-14 11:08:54

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File Size: 203,57 KB

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City

Berlin / /

Company

John Wiley & Sons Inc. / Helion Technology / Patterson / BX SRL / CAST Inc. / Xilinx / Advances / /

Country

Belgium / /

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Facility

Prentice Hall / FIPS PUB / Pipeline Xil / /

IndustryTerm

route tool / with limited hardware / computing / This solution / /

Person

Jean-Didier Legat / Jean-Jacques Quisquater / CIN LUT LUT / Xavier Standaert / Chaum / /

Position

editor / /

PublishedMedium

IEEE Transactions on Computers / /

Region

Levant / /

Technology

encryption / FPGA / cryptography / triple-Data Encryption / Virtex-E technology / Using Virtex-II technology / Accelerator Board / DES algorithm / 2 The DES algorithm / Gigabit / VirtexII technology / VHDL / Integrated Circuits / /

URL

http /

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