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Modeling and Verifying Hierarchical Real-time Systems using Stateful Timed CSP1 Jun Sun, Yang Liu Singapore University of Technology and Design ´ Jin Song Dong, Yan Liu, Ling Shi and Etienne
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Document Date: 2011-05-04 10:00:40
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Modeling and Verifying Hierarchical Real-time Systems using Stateful Timed CSP1 Jun Sun, Yang Liu Singapore University of Technology and Design ´ Jin Song Dong, Yan Liu, Ling Shi and Etienne