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1 A Digital Neurosynaptic Core Using Embedded Crossbar Memory with 45pJ per Spike in 45nm Paul Merolla1 , John Arthur1 , Filipp Akopyan1,2 , Nabil Imam2 , Rajit Manohar2 , Dharmendra S. Modha1 1 IBM Research - Almaden,
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Document Date: 2011-10-06 17:50:51

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File Size: 2,20 MB

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City

Boston / New York / /

Company

IBM / Scott Fairbanks / AddisonWesley Longman Publishing Co. Inc. / /

Country

United States / /

Facility

Scott Hall / /

IndustryTerm

above specification in hardware / neural algorithm / off-chip / neural network algorithms / software simulation / nano-devices / sequential processing model / dense technology / software network / software model / software models / neuromorphic computing / large-scale brain-like networks / real-time applications / biological systems / neural networks / rhythmic spiking network / recurrent network / analog neuromorphic systems / large on-chip network / software simulator / non-deterministic routing network / project management / neural systems / Active energy / software activity / software development / prototype chip / hardware-implementable neural algorithms / /

Organization

ASIC / U.S. Government / Cornell University / /

Person

Steven Esser / Carlos Otero / Kavita Prasad / Spike / Jon Tse / Andrew Cassidy / Sue Gilson / Ben Hill / Greg Corrado / Rodrigo Alvarez / Rob Karmazin / Ben Johnson / /

Product

45nm SOI / /

Technology

neuroscience / neural network algorithms / CMOS technology / ASIC / off chip / prototype chip / 250 Simulation Chip / same technology / hardware-implementable neural algorithms / neural algorithm / SRAM / simulation / dense technology / /

URL

http /

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