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City Santa Clara / Controller / Lake City / Barcelona / Urbana / Boston / Philadelphia / Portland / Amsterdam / Toronto / / Company Hewlett-Packard / Control Data / / Country Netherlands / Canada / Australia / Spain / / Facility Computer Science yIntel Corporation University of Utah Dupont / / IndustryTerm compiler algorithms / regular applications / conventional systems / matrix product / conventional memory systems / non-scientific applications / Sparse matrix-vector product / message passing systems / matrix-matrix product / dynamic access ordering hardware / simplest tiled algorithm / large scientific algorithms / signal processing / bank conflicts / memory systems / controller hardware / commodity processors / tiled matrix-matrix product / vector applications / matrix-vector product / memory-bound applications / irregular applications / dense matrix-matrix product / important applications / software tile copying / tiled matrix algorithms / matrix algorithms / multi-bank memories / vector processors / bank-level parallelism / sparse matrixvector product / / MarketIndex COLUMN / / OperatingSystem BSD / / Organization MIT / Computer Science yIntel Corporation University of Utah Dupont / NASA Ames Research Center / / Person Chris Johnson / Michael Parker / Mark Swansony / Chen-Chi Kuo / John Carter / Terry Tateyama / Al Davis / Using Impulse / Leigh Stoller / Llewellyn Reese / Massimiliano Poletto / Wilson Hsieh / Erik Brunvand / Sally McKee / Lambert Schaelicke / / Position lowlevel DRAM scheduler / Smarter Memory Controller / DRAM scheduler / interpreter / conventional memory controller / model / Scheduler / simple scheduler / memory controller / controller / / Product RISC 1.1 processor / RISC 1.1 / / ProgrammingLanguage C / / ProvinceOrState Illinois / Oregon / Utah / Pennsylvania / California / Massachusetts / / Technology simplest tiled algorithm / actual DRAM chips / large scientific algorithms / commodity processors / vector processors / SRAM / operating system / shared memory / operating systems / compiler algorithms / 1.1 processor / tiled matrix algorithms / Matrix Algorithms Dense matrix algorithms / caching / simulation / Virtual Memory / DRAM chips / 2000 processor / CAD / / SocialTag 
Impulse: Building a Smarter Memory Controller John Carter, Wilson Hsieh, Leigh Stoller, Mark Swansony, Lixin Zhang, Erik Brunvand, Al Davis, Chen-Chi Kuo, Ravindra Kuramkote,