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NVAX / Instruction set architectures / VAX 7000/10000 / VAX / Alpha 21064 / DEC Alpha / CPU cache / VAXft / CVAX / Computer hardware / Computer architecture / Computing


The NVAX and NVAX+ High-performance VAX Microprocessors By G. Michael Uhler, Debra Bernstein, Larry L. Biro, John F. Brown III, John H. Edmondson, Jeffrey D. Pickholtz, and Rebecca L. Stamm
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Document Date: 2003-03-18 13:28:40


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File Size: 44,26 KB

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IndustryTerm

cache protocols / directory-based broadcast coherence protocol / bus protocol / on-chip / metal-oxide semiconductor / low-skew clock distribution network / /

Person

G. Michael Uhler / Larry L. Biro / Rebecca L. Stamm / John F. Brown III / Debra Bernstein / John H. Edmondson / Jeffrey D. Pickholtz / /

Position

system designer / /

Technology

semiconductor / Alpha / RAM / NVAX chip / NDAL bus protocol / chip design / two NVAX chips / Physical Design Process technology / 4 Chip / NVAX+ chip / directory-based broadcast coherence protocol / bus protocol / two CPU chips / two chips / The NVAX chip / NVAX+ CPU chips / NVAX+ chips / cache protocols / /

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