First Page | Document Content | |
---|---|---|
Date: 2013-10-28 13:05:49Integrated circuits Logic families MOSFET Subthreshold slope CMOS Dynamic voltage scaling Field-effect transistor Transistor Subthreshold conduction Electronic engineering Electronics Technology | UT DALLAS Erik Jonsson School of Engineering & Computer ScienceAdd to Reading ListSource URL: www.stanford.eduDownload Document from Source WebsiteFile Size: 2,78 MBShare Document on Facebook |
PDF DocumentDocID: 1xs12 - View Document | |
PDF DocumentDocID: 1x2IS - View Document | |
DOC DocumentDocID: 1wpoX - View Document | |
A 23mW Face Recognition Accelerator in 40nm CMOS with Mostly-Read 5T Memory Dongsuk Jeon1,2, Qing Dong1, Yejoong Kim1, Xiaolong Wang3, Shuai Chen3, Hao Yu3, David Blaauw1, Dennis Sylvester1 1 University of Michigan, MI;DocID: 1vrMD - View Document | |
CELL CULTURE COURSE PROGRAM September 13, 2014 08:00-08:45 Cultivation of cells, passaging, Medium Preparation and Preparation for experiments Theoretic 09:00-09:45 Cultivation of cells, passaging, Medium PreparatiDocID: 1vnJh - View Document |