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![]() | Document Date: 2008-10-28 11:49:02Open Document File Size: 125,91 KBShare Result on FacebookCityISR / PMU / /CompanySynopsys / ALTERA / Evatronix SA / TSMC / I High Hardware / MTI / /CountryPoland / / /EventNatural Disaster / /FacilitySerial1 port / PORT Port / Serial Port / O High Program store / I Verification Methods Serial Port / I/O port / Artisan TSMC library Copyright / Headquarters Przybyly / / /IndustryTermcontrol algorithm / software breakpoints / low-power control systems / on-line hardware / 80C51 device / e.g. energy / /NaturalFeatureRise/Fall / /OrganizationFPGA / Power Management Unit / ASIC / Central Processing Unit / Data Sheet Design Department / /PersonClock Peripheral / / /Position80C515-compatible Interrupt Controller / port controller / behavioral model / Controller / Data Sheet Pin Description Name Performance Polarity/ Type Bus size Description General / /ProductSDI iP1 Speakers / /ProgrammingLanguageVerilog / /TechnologyFPGA / Third Party Reference The T8051 On-Chip / full-duplex / RAM / ASIC / Verilog / FLASH memory / JTAG / control algorithm / generator On-Chip / simulation / 4 T8051 Data Sheet Block Diagram T8051_CPU External Memory Interface On-Chip / DSP / 0 external input On-Chip / UART / /URLwww.evatronix.pl / /SocialTag |