Date: 2012-09-06 23:52:12Parallel computing Thread Multithreading Multi-core processor Task parallelism SPMD CPU cache Cell Message Passing Interface Algorithmic skeleton | | Resource-Efficient, Hierarchical Auto-Tuning of a Hybrid Lattice Boltzmann Computation on the Cray XT4 Samuel Williams? , Jonathan Carter? , Leonid Oliker? John Shalf? , Katherine Yelick?† ? CRD/NERSC, Lawrence BerkeleAdd to Reading ListSource URL: crd.lbl.govDownload Document from Source Website File Size: 443,38 KBShare Document on Facebook
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