Reservation Station / Store Data Store Load Addr / Resource stalls / stall CPI / Computer Science Division University of California at Berkeley / LOAD STORE / Fetch Unit IN-ORDER Up Sequencer SECTION Reservation Station / Soda Hall / /
IndustryTerm
given processor / experimental infrastructure / parallel computing market / branch prediction algorithms / active processors / software runs / out-of-order processors / processor chip / transaction processing / 21164based server / Online Dynamic Server / transaction processing database workloads / database server / configured systems / server applications / online transaction processing / cache coherence protocol / on-chip / /
MarketIndex
OLTP / /
OperatingSystem
Windows NT 4.0 / /
Organization
University of California / GB Memory / Transaction Processing Council’s TPC / Transaction Processing Council / /
Person
Kimberly Keeton / David A. Patterson / Yong Qiang He / Roger C. Raphael / Walter E. Baker / /
Position
RAT RRF Simple Decoder General / representative / forward / memory controller / controller / /
Product
Pentium Pro processor / Pentium Pro / L2 / /
ProvinceOrState
Manitoba / California / /
Technology
Alpha / branch prediction algorithms / symmetric multiprocessing / Pentium Pro processor / four processors / given processor / out-of-order processors / processor chip / random access / operating system / active processors / four-state MESI cache coherence protocol / 8 KB on-chip / simpler three-state protocol / 200 MHz Pentium Pro processors / caching / simulation / Characteristic Base System Processor / SCSI / /
To appear in Proceedings of the 25th International Symposium on Computer Architecture, Barcelona, Spain, June[removed]Performance Characterization of a Quad Pentium Pro SMP Using OLTP Workloads Kimberly Keeton*, David A.